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[VHDL-FPGA-Verilog] i2c

Description: VHDL语言编写的I2C core，已经验证通过！-VHDL language I2C core, has already been verified through!
Platform: | Size: 351232 | Author: gelim_w | Hits:

[VHDL-FPGA-Verilog] designgamebasedonFPGA

Description: Run Pac-man Game Based on 8086/8088 FPGA IP Core
Platform: | Size: 432128 | Author: wangwei | Hits:

[VHDL-FPGA-Verilog] EP2C5Q208

Description: 以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等-Cyclone in series as the core EP2C5Q208 experimental procedure. Including water lights, I2C memory. SPI memory, digital control, serial port, LCD, etc.
Platform: | Size: 2980864 | Author: sarah | Hits:

[ARM-PowerPC-ColdFire-MIPS] or2000

Description: 这是一个MIPS架构的开发的CPU软核OR2000，比OR1200更高的版本，里面还有SOC程序，多次MPW流片成功-This is a MIPS architecture to develop the CPU soft-core OR2000, higher than OR1200 version, there is also SOC procedures, many times MPW silicon success
Platform: | Size: 102400 | Author: liming | Hits:

[VHDL-FPGA-Verilog] Nios

Description: nois 2cpu 硬件实现编程，在fgja上实现软核-nois 2cpu hardware programming, in the realization of soft-core fgja
Platform: | Size: 1173504 | Author: xiaohuaifeng | Hits:

[Other] free_IP_1

Description: 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
Platform: | Size: 2644992 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库 第二章 调用Xilinx CORE-Generator 第三章 使用Synplify.Pro综合HDL和内核 第四章 综合后的项目执行 第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Platform: | Size: 218112 | Author: 青岚之风 | Hits:

[VHDL-FPGA-Verilog] 8051Core

Description: 8051IP内核的源码，内有vhdl源代码，希望对大家有帮助-8051IP kernel source code, with VHDL source code, I hope all of you help
Platform: | Size: 1146880 | Author: sylivian | Hits:

[VHDL-FPGA-Verilog] BFSK_VHDL_CODING

Description: 使用DDS技术，应用altera公司的芯片，以及杭州康芯公司的试验箱，实现BFSK信号的调制解调-The use of DDS technology, applications altera chips, as well as the core company in Hangzhou, Culture and Sport chamber, the realization of BFSK signal modulation and demodulation
Platform: | Size: 265216 | Author: 叶峰 | Hits:

[SCM] 8051_core_VHDL

Description: Vhdl硬件描述语言例子集，含8051内核的源码-VHDL hardware description language examples set, containing 8051 kernel-source
Platform: | Size: 1058816 | Author: 黄豆 | Hits:

[VHDL-FPGA-Verilog] 8255

Description: Verilog语言描述的Intel8255 IP Core，本人已经在某项目中经过了物理验证的，可直接用于FPGA综合或ASIC综合。
Platform: | Size: 6144 | Author: David.Mr.Liu | Hits:

[Graph program] quantizer

Description: 这个DCT的源代码Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA-The DCT of source code Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA
Platform: | Size: 51200 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[Graph program] dct

Description: this si Arithmetic core,it contains FreeDCT-L and FreeDCT-M.FreeDCT-L is a low power architecture 1-Dimensional 8-point DCT/IDCT core.FreeDCT-M is a moderate speed 1-Dimensional IDCT core
Platform: | Size: 866304 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] mc_8051

Description: 该源代码是实现了8051 mcu core的VHDL代码，中断、计时等各功能全面，且包括了各部分的详细测试文件-The source code is to achieve a 8051 mcu core of the VHDL code, interrupt, timer and other full-featured, and includes details of the various parts of the test document
Platform: | Size: 657408 | Author: swelgan | Hits:

[VHDL-FPGA-Verilog] basicforVHDLIPcoretest

Description: 基于VHDL语言的IP核验证 -VHDL-based IP core verification language
Platform: | Size: 8192 | Author: 张波 | Hits:

[Streaming Mpeg4] rs_enc

Description: 使用IP Core实现了3GPP/UMTS所规定的Turbo码编码，可以在Virtex全系列和Spartan-3E等芯片上使用，最多支持１６路信号，能提供3GPP所要求的1/3码率输出和可选的1/5码率输出-Use IP Core achieved 3GPP/UMTS provided for Turbo-Coded, you can Virtex series and Spartan-3E chip such as the use, supports up to 16-way signal, 3GPP can provide the required 1/3 bit-rate output and optional 1/5 Rate Output
Platform: | Size: 1024 | Author: 刘横 | Hits:

[VHDL-FPGA-Verilog] Uart

Description: 用ＦＰＧＡ，VHDL实现的Uart核，quartusII完整工程，实用-Using FPGA, VHDL realize the UART core, quartusII complete projects, practical
Platform: | Size: 631808 | Author: wanyou | Hits:

[VHDL-FPGA-Verilog] Example-b3-1

Description: 使用Quartus II设计FPGA的应用设计实例  “\Example-b3-1\uart_regs\src”目录下为设计源文件  “\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块  “\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件  “\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件  “\Example-b3-1\uart_regs\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
Platform: | Size: 397312 | Author: king | Hits:

[Other] EHERNETIPcore

Description: 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
Platform: | Size: 69632 | Author: season | Hits:
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